The present invention relates generally to low dropout (LDO) linear voltage regulators of the kind having P-channel pass transistors, i.e., PMOS LDO linear voltage regulators. The invention also relates more particularly to such LDO voltage regulators having very low quiescent current and good phase margin despite large variations in the load and the output capacitance.
Various approaches have been used to address the problems associated with providing such LDO voltage regulators having low quiescent current, as is desirable for battery-powered applications in order to extend battery operating life. In some LDO voltage regulator designs, the P-channel pass transistor is driven by a voltage buffer which pushes the pole associated with the gate capacitance beyond the unity-gain frequency of the feedback loop of the voltage regulator. However, that technique is not suitable for PMOS LDO regulators that need to have a very low quiescent current.
Instead of dissipating a large amount of quiescent current in a voltage buffer as mentioned above, adding a zero in the voltage transfer characteristic of the regulator feedback loop may cancel the pole either from the gate capacitance of the PMOS pass device or from the output capacitor. In some cases, the zero can be obtained by using output capacitors with high equivalent series resistance (ESR). Nevertheless, the “ESR zero” type of compensation provided by the output capacitor is not very efficient in low quiescent current LDO regulator design, especially for the popular low ESR ceramic capacitors whose ESR zeros are far outside of the narrow bandwidth of the low bandwidth characteristic of low quiescent current LDO voltage regulators. Therefore, the “compensation zero” has to be created within the LDO feedback loop in most cases.
Adding a “compensation zero” type of compensation within the LDO feedback loop can achieve very good pole-zero cancellation if the specific values of the LDO voltage regulator output capacitance and its ESR are known. However, because of the wide ranges of output capacitance and the associated ESR values, the zero added into the transfer characteristic of the feedback loop always provides incomplete compensation under certain conditions, resulting in LDO regulator instability.
Referring to FIG. 1, a conventional PMOS linear voltage regulator 1 includes a P-channel pass transistor MPpass which operates as a current source controlled by an error amplifier 2 having a transconductance gmi. The capacitance C1 connected between the gate and source of pass transistor MPpass is CCH+Cgs (the sum of the channel capacitance CCH and gate-source overlap capacitance Cgs), and Cc is the gate-drain overlap capacitance Cgd. For short channel transistors, Cgs and Cgs are comparable to CCH. The transconductance gmo of pass transistor MPpass is a function of the load current IL flowing out of the drain of the pass transistor. It should be noted that without a voltage buffer of the kind mentioned above, the conductor 3 connected to the gate of pass transistor MPpass is a gain node which presents a pole. The pole is related to the gate capacitance of pass transistor MPpass and the output resistance rol of error amplifier 2. The load capacitance CL provided by the user causes another pole that is inversely proportional to the product of CL and RL, where RL is the small signal resistance seen at conductor 4 and includes the load resistance, the divider, and the output resistance ro of pass transistor MPpass.
Therefore, the PMOS LDO voltage regulator 1 in FIG. 1 is a two-pole system which may have very low phase margin under certain load conditions. Due to the different natures of various applications, the equivalent AC load may be either a passive load such as a resistor or an active load such as a current source. The uncertainty regarding the AC impedance of the load makes the design of PMOS LDO voltage regulator 1 very difficult, because the output pole has a strong dependence on the equivalent AC load. Nevertheless, in almost all situations the DC gain gmoRL from the gate conductor 3 to the output conductor 4 is much greater than 1 (i.e., gmoRL>>1), which is quite different from the N-channel pass transistor case in which the NMOS source follower provides a DC gain very close to unity.
The AC voltage gain vo/vi (where vo is Vout and vi is Vin) of the loop can be found as follows, for CL>>Cc:
                                          v            o                                v            i                          =                                                            g                mi                            ⁢                              r                01                            ⁢                              g                mo                            ⁢                                                R                  L                                ⁡                                  (                                      1                    -                                                                  sC                        c                                            /                                              g                        mo                                                                              )                                                                    1              +                              s                ⁡                                  [                                                                                    C                        L                                            ⁢                                              R                        L                                                              +                                                                  (                                                                              C                            1                                                    +                                                      C                            c                                                                          )                                            ⁢                                              r                        01                                                              +                                                                  g                        mo                                            ⁢                                              R                        L                                            ⁢                                              C                        c                                            ⁢                                              r                        01                                                                              ]                                            +                                                s                  2                                ⁢                                  r                  01                                ⁢                                                      R                    L                                    ⁡                                      (                                                                  C                        1                                            +                                              C                        c                                                              )                                                  ⁢                                  C                  L                                                              .                                    Eq        .                                  ⁢                  (          1          )                    From the denominator of Eq. (1) it can be seen that there are two poles. For any particular design, the values of C1, Cc, and rol are given and the poles are functions of CL and RL. Instead of solving Eq. (1), the manner in which the magnitudes and phases of the poles change with respect to CL and RL can be determined for a fixed value of load resistance RL. For a very large CL, the dominant pole p1 and the non-dominant pole p2 are obtained by factoring the second-order denominator as:
                                                        p              1                        =                          1                                                C                  L                                ⁢                                  R                  L                                                              ,          and                ⁢                                  ⁢                              p            2                    =                                    1                                                (                                                            C                      1                                        +                                          C                      c                                                        )                                ⁢                                  r                  01                                                      .                                              Eq        .                                  ⁢                  (          2          )                    (For more information, see page 241 et seq. of “Analog Integrated Circuit Design”, by D. Johns, and K. Martin, John Wiley & Sons, 1997.) However, for very small CL, the dominant pole p1 and the non-dominant pole p2, respectively, are given by:
                                                        p              1                        =                          1                                                g                  mo                                ⁢                                  R                  L                                ⁢                                  C                  c                                ⁢                                  r                  01                                                              ,          and                ⁢                                  ⁢                              p            2                    =                                                    g                mo                                            C                L                                      ×                                                            C                  c                                                                      C                    1                                    +                                      C                    c                                                              .                                                          Eq        .                                  ⁢                  (          3          )                    Sketches of poles p1 and p2 versus CL for a fixed RL are shown in FIG. 2A. For a very small value of load capacitance CL, the value of the dominant pole p1 does not change with CL and can be attributed to the Miller capacitor Cc, and the value of non-dominant pole p2 moves away from that of the dominant pole p1 as the capacitance CL decreases, as shown in FIG. 2A. On the other hand, for a very large CL, the dominant pole p1 is attributed to CL and it moves away from the non-dominant pole p2 which stays at
  1            (                        C          1                +                  C          c                    )        ⁢          r      01      as CL increases. The magnitudes of poles p1 and p2 are the closest when CL=gmorolCc indicating that the load capacitor and the Miller capacitor pole have the same amount of delay and neither is dominant. Under that worst case condition,
                                                        p              1                        =                                          1                                                      g                    mo                                    ⁢                                      R                    L                                    ⁢                                      C                    c                                    ⁢                                      r                    01                                                              =                              1                                                      C                    L                                    ⁢                                      R                    L                                                                                ,          and                ⁢                                  ⁢                              p            2                    =                                    1                                                (                                                            C                      1                                        +                                          C                      c                                                        )                                ⁢                                  r                  01                                                      .                                              Eq        .                                  ⁢                  (          4          )                    
The worst case Q factor is
                                          Q            =                                                            [                                                                                    A                        0                                            ⁢                                              p                        1                                                                                    p                      2                                                        ]                                                  1                  /                  2                                            =                                                [                                                            g                                              m                        ⁢                                                                                                  ⁢                        i                                                              ⁢                                          r                      01                                        ⁢                                                                  C                        c                                                                                              C                          1                                                +                                                  C                          c                                                                                                      ]                                                  1                  /                  2                                                              ,          where                ⁢                                  ⁢                              A            0                    =                                    g                              m                ⁢                                                                  ⁢                i                                      ⁢                          r              o                        ⁢                          g              mo                        ⁢                                          R                L                            .                                                          Eq        .                                  ⁢                  (          5          )                    This is for the case in which the feedback loop has unity gain. In Eq. (5), A0=gmirogmoRL is the overall DC gain of the loop.
The foregoing analysis reveals the poles changing with CL for a fixed load RL. However, in a typical LDO application, the load changes while CL is provided by the user and kept as a constant. Thus, it would provide a better insight to analyze the poles changing with load RL, or gmo, for a fixed CL. Nevertheless, plotting poles p1 and p2 versus gmo is not as straightforward as plotting them versus CL because gmo and RL have no simple relationship. The complexity results not only from the strong application dependencies of RL as pointed out previously, but also from the nonlinear dependency of gmo on the load current IL flowing out of the drain of pass transistor MPpass. In fact, gmo is proportional to IL when pass transistor MPpass is in sub-threshold operation for a very light load current, whereas it is proportional to (IL)1/2 when the pass transistor MPpass is in saturation for a heavy load current. However, in the current range in which the two capacitors “fight for dominance”, pass transistor MPpass is still in sub-threshold operation, which will be shown later. In the sub-threshold operating region, gmoRL can be taken as a constant because gmo is proportional to IL while RL is inversely proportional to IL.
Again, by using a similar asymptotic approach, poles p1 and p2 can be derived by factoring the denominator of Eq. (1) and are given by Eq. (2) for small gmo (or large RL) and by Eq. (3) for large (or small RL), respectively. Based on Eqs. (2) and (3), poles changing with gmo can be sketched as in FIG. 2B, assuming gmoR1 is a constant. For a small value of gmo, the dominant pole p1 can be attributed to the load capacitor CL and its value moves away from the value of the non-dominant pole p2 as gmo decreases (or as RL increases) while pole p2 stays at
      1                  (                              C            1                    +                      C            c                          )            ⁢              r        01              .On the other hand, for a large value of gmo, the value of dominant pole p1 does not change with gmo and can be attributed to the Miller capacitor Cc, and the value of non-dominant pole p2 moves away from pole p1 as gmo increases. The magnitudes of poles p1 and p2 are the closest when
                                          g            mo                    =                                    C              L                                                      C                c                            ⁢                              r                01                                                    ,                            Eq        .                                  ⁢                  (          6          )                    wherein the load capacitor and the Miller capacitor cause the same amount of delay and neither of them is dominant. Under that condition, the LDO regulator feedback loop has its lowest phase margin, with the pole locations and the Q factor given by Eqs. (4) and (5), respectively.
Not surprisingly, both analyses, poles vs CL and poles vs gmo, give the same worst case condition. To summarize, poles p1 and p2 can be attributed to CL and Cc only when poles p1 and p2 are widely separated. For small gmo, p1 can be attributed to the load capacitor pole; for large gmo, p1 can be attributed to the Miller capacitance pole. For gmo around the value give by Eq. (6), p1 can not be attributed to either of them.
It also can be seen from Eq. (2) and Eq. (3) that the curves of poles p1 and p2 versus gmo shift horizontally for different values of the user-provided load capacitance CL. Poles p1 and p2 versus gmo with a larger value of CL are shown as dashed lines in FIG. 2B. Since the worst case Q factor is independent of CL, there is always a minimum phase margin at a certain load condition for whatever load capacitance is being used.
FIG. 3 shows the simulated phase margins at unity gain versus load current for CL=μF (Curve A), 10 μF (Curve B), and 100 μF (Curve C) for the simple topology PMOS LDO of FIG. 1, illustrating the existence of a minimum phase margin irrespective of load capacitance. Curves A, B and C exhibit approximately 1 degree of phase margin at load currents IL of 300 nA, 3 uA, and 30 uA for CL=1 μF, 10 μF, and 100 μF respectively. With those currents, the pass transistor MPpass with a W/L ratio of 50,000 microns/0.8 micron, still operates in its sub-threshold region, which supports the assumption that gmoRL is a constant.
FIGS. 4A-C show the overall open loop gain Bode plots as solid lines for the simple LDO topology, representing the cases (a) when the output capacitor dominates the frequency response, i.e.,
            1                        C          L                ⁢                  R          L                      <          1                        g          mo                ⁢                  R          L                ⁢                  C          c                ⁢                  r          01                      ;(b) when the output capacitor and the Miller capacitor are equally strong in frequency response, i.e.,
            1                        C          L                ⁢                  R          L                      =          1                        g          mo                ⁢                  R          L                ⁢                  C          c                ⁢                  r          01                      ;and (c), when the Miller capacitor dominates,
            1                        C          L                ⁢                  R          L                      >          1                        g          mo                ⁢                  R          L                ⁢                  C          c                ⁢                  r                      o            ⁢                                                  ⁢            1                                ,respectively. The dashed lines 9-4 and the dot-dash lines 9-2 indicate the gains from the pass transistor gate to the output and from the input of error amplifier 2 to its output, respectively. In FIG. 4A where the output capacitor dominates, the corner frequency 1/(CLRL) of curve 9-4, is on the left hand side of the corner frequency of curve 9-2. The product of curve 9-2 and curve 9-4 gives the overall open loop gain, 9-1. FIGS. 4B and 4C can be analyzed similarly.
In summary, the prior art PMOS LDO voltage regulator of FIG. 1 possesses significant stability shortcomings. It has been shown that under the worst case condition, the Q factor of the closed loop is given by Eq. (5) as [gmirolCc/(Cc+C1)]1/2. Q could be as large as approximately 30, since gmirol could be 60 to 70 dB while Cc/(Cc+C1 is on the order of 1, implying a very low phase margin and, as demonstrated in FIG. 3, leading to very poor transient performance under the worst case condition.
Thus, there is an unmet need for a PMOS LDO voltage regulator which has ultra-low quiescent current and which provides stable operation substantially irrespective of the load supplied thereby.